The present invention relates generally to digital dividers, and more particularly to devices and methods able to estimate a digital quotient of several bits in about 5 to 500 clock cycles.
Fast digital dividers generally fall into one of two categories: calculation-type and lookup-type. Although designing logic to calculate a quotient with greater precision is not difficult, the number of gates becomes exponentially more costly for each additional bit of precision required. As a result, calculation-type dividers typically provide only a few bits of precision.
Lookup-type dividers receive an input that combines the numerator and denominator. They then output a quotient retrieved from a table, typically implemented in read-only memory (ROM). Like the logic of calculation-type dividers, expanding ROM to enhance precision is not complex but quickly become unwieldy as precision increases further.
As a result, applications which require greater precision often resort to doing so in software. This greatly reduces the speed with which division can be performed. For ascertaining quotients in time-critical applications such as a motion controller that senses its position each millisecond, there is a continuing need for a precise digital divider that is faster than a code-implemented divider and more precise than a typical calculation-type or lookup-type divider.
Devices and methods are provided for estimating a quotient efficiently, using a table that is smaller than that of a conventional lookup-type divider of a like precision. The devices include a numerator register feeding a succession of bits or words comprising the numerator value into a forward signal path. The forward path includes a partial quotient generator (PQG) able to generate a succession of signals indicative of portions of the quotient. After passing through an accumulator, each partial quotient is then latched. The devices further include a bit-shifting feedback signal path emerging from the latch output and terminating into another input of the accumulator. The devices further include control circuitry for triggering the numerator register(s) and/or the latch(es) to change state.
Methods of the present invention include steps of receiving a numerator and a denominator each as a digitized value, parsing the numerator, providing at least a portion of the numerator with the denominator to a PQG, and latching the output. The methods further include reducing the result approximately by a factor of about 2 (or 4 or some larger power of two) summing the reduced result with at least one additional value obtained from the PQG.
A most preferred device of the present invention finds advantageous use in a disc drive servo control system, the device calculating a formula taking the general form (F/G)/(F/G+H/J).